Part -1:
Question 1.
(a) Performance of a system is the reciprocal of execution time. Justify the statement.
(b)A 4GHZ machine is designed to runs a graphics program. Its observed that 20% of instructions are ALU instruction,40% are I/O instruction and the rest are the data transfer instruction. If ALU instructions take 5 clock cycle JO instructions take 8 clk cycle and data transfer instruction take 7 clk cycle. Then find the average CPU time and CPI of the program.
(c) Find the accuracy rate of 2bit prediction for the following actual output sequence T T T T T NT NT NT.assume the initial prediction bit is 00.
(d) Define antidependancy with the help of suitable example.
(e) What is the use of register renaming explain with suitable example ?
Question 2. What is pipeline. Explain the implementation of five stage pipeline for MIPS machine.
Question 3. Consider the following set of instruction
LD R1 ,m[2230]
DADD R2,R1,R3
DSUB R4,R1,R5
AND R6,R1,R7
OR R8,R1,R9
Identify the type of hazard arises between the instruction. Find the number of stall arises due to hazard. What technique should be used to reduce this delay.
Question 4. What is Amdahl's law ?To enhance the 3D video application a new processor is designed which is 20 times faster than the original processor. if the older processor is busy with 20% computational task and is waiting for 80% of the time, what is the overall speed up gained by incorporating the enhancement.
Question 5. What is loop Unrolling. How to use scheduled loop unrolling technique to minimize the number of cycle per instructions for the sequence.
Loop: LD FO, 0(R1)
ADDD F4, F0,F2
SD 0(R1), F4
SUBI R1, R1,#8
BENZ R1, Loop
Part-2
1. a) Discuss different functional units of a digital computer system with its block diagram.
b) A relative mode branch type instruction is stored in memory at an address 750. The branch is made to an address 500. What should be the value of the relative address field of the instruction?
c) What is difference between write-through and write-back protocol?
d) A computer has 58 instructions; each instruction requires at most 15 steps to complete its execution. What will be the specification of instruction and step counter decoder used in hardware control unit design?
e) A processor is connected to 256GX32 memory module. What is the size of MAR and MDR registers?
PART-B
2. a) Explain Basic-Operational-Concepts of a computer system with the help of a block diagram.
b) Write down the sequence of instructions for the execution of the following statement: X = (A-B)*(C+D) using,
a. Zero addresses instructions b. One address instructions
c. Two address instructions d. Three address instructions
3. a) Discuss multi bus organization of a data path inside a processor with the help of a block diagram. Write down the control sequence of the instruction ADD (R1), R2, R3 in three-bus organization, where (R1), R2 are used as source operand and R3 is used as destination operand.
b) An instruction is stored at location 500 with its address field at location 501. The address field contains the value 80. The contents of a processor register R1 and an Index Register XR are 501 and 321 respectively. Determine the effective address and data operand (if any), if the addressing mode of the instruction is: (i) Direct (ii) Immediate (iii) Register indirect (iv) Relative (v) Index
4.
a) Outline the design principle of a hardwired control unit with necessary block diagram.
b) Explain the operation of single-bus organized processor with necessary diagrams and its advantages and disadvantages over multi bus organized processor.
5. Write Short notes on any two of the following:
i. Memory Hierarchy and Locality-of-reference
ii. Arithmetic, Logical and Shift Instructions
iii. Microprogrammed control unit