Synchronized shift-register outputs Consider again the diagram of Figure E14.30(a), but suppose that now the output x comes from a circular shift register, whose rotating sequence is initialized with "1000". Suppose also that the sequence y must be delayed with respect to x by one clock period (so y should be initialized with "0001"). A (bad) solution analogous to that in Figure E14.30(b) could be employed, requiring two circular SRs. As in the exercise above, devise a better circuit that solves this problem.
