A serial parity bit generator is a sequential circuit that does the following: It receives an N-bit message followed by a zero (so there are N+1 clock bits to send the message). At the output the circuit sends the original N-bit message but replaces the zero with a parity bit. Design a four bit serial parity bit generator which replaces the zero with an odd parity bit.
A) Draw a state diagram for the circuit
B)Draw a state transition table for the circuit
C) Show how to implement the circuit using D flip flops.
D)Write a verilog program for the circuit
E)Mealy or moore machine? Why?