A low-power ttl logic gate with an active pnp pull-up

Question

A low-power TTL logic gate with an active pnp pull-up device is shown in Figure. The transistor parameters are β_F = 100 and β_R = 0.2 (for each input emitter). Assume a fanout of 5.

(a) For v_X = v_Y = v_Z = 0.1 V, determine i_B1, i_B2, i_B3, i_C2, and i_C3.

(b) Repeat part (a) for v_X = v_Y = v_Z = 2 V.