A logic family has a power-delay product of 100 fj if a

Question

A logic family has a power-delay product of 100 fJ. If a logic gate consumes a power of 100 W, what is the expected propagation delay of the logic gate? The graph in Fig. P6.135 gives the results of a SPICE simulation of an inverter.

(a) What are the rise and fall times for v_I and v_O?

(b) What are the values of τ_PHL and τ_PLH? (c) What is the average propagation delay for this gate?