Consider a static CMOS inverter that can drive a capacitive load of 0.05pF.
Assume the following parameters:
VDD = 3 volts,
Vtn = - Vtp = 0.7 volts,
K'n= 120 A/volts2
K'p= 60 A/volts2
The length of the n-channel and the p-channel are Ln = Lp = 0.8 m.
Assume that the p-channel is twice as wide as the n-channel.
a) It is required that the propagation delay be limited to 60 psec. Find the required device widths
b) Find the High and Low noise margins, i.e. NMH and NML.
c) What is the peak current drawn from VDD during switching of the inverter?
What is the average current drawn from the power supply?
d) What is the dynamic power dissipation that results when the inverter is switched at a frequency of 2 MHz?