Question: A circuit has four inputs RSTU and four outputs VWYZ. RSTU represents a binarycoded- decimal digit. VW represents the quotient and YZ the remainder when RSTU is divided by 3 (VW and YZ represent 2-bit binary numbers). Suppose that invalid inputs do not occur.
Realize the circuit using
Part 1: a ROM
Part 2: a minimum two-level NAND-gate circuit
Part 3: a PLA (specify the PLA table)
Make sure to show all your work - Provide answer with example.