A block diagram and state graph for a divider for unsigned binary numbers is shown below. This divider divides a 16-bit dividend by a 16-bit divisor to give a 16-bit quotient. The divisor can be any number in the range 1 to 216 - 1. The only case where an overflow can occur is when the divisor is 0. Control signals are defined as follows: Ld1: load the divisor from the input bus; Ld2: load the dividend from the input bus and clear ACC; Sh: left shift ACC & Dividend; Su: load the subtractor output into ACC and set the lower quotient bit to 1; K = 1 when 15 shifts have been made. Write complete VHDL code for the divider. All signals must be of type unsigned or bit. Use two processes.
