3-bit Serial in, Parallel out Shift Register with asynchronous active low reset Requirement:
-use rising edge D-ff(D flip flop) with asynchronous active low reset
-D-ff should use 4 Transmission gates in its implememtation
-each D-ff should use only 3 inputs and 2 output max.
(Input: D, clk, reset/ active low, Output:Q, )
-Implement in 120 µm technology
-need to reasonably minimize area of D-ff& S/R
-Run DRC(Design rules checking) should have 0 DRC violations
-Do layout manually
-Simulate D-ff& S/R
-use "DSCH"Schemetic editor to capture schematic & test
-Can use Microwind(for layout) or other tool for layout
What you need to sumbit:
1)Block Diagram of S/R & D-FF
2)Transistor level Schametic of D-ff& S/R
3)Functional simulation of D-ff& S/R waveform(enough clock cycles & pattern to demonstrate proper operation)
4)Layout of D-ff& S/R (in color & large)
5)DRC results on D-ff& S/R
6)Area calculation of D-ff& S/R