1.Design a finite state machine (FSM) that transitions from 0 to 2 to 4 to 5 to 7 to 0. Write the VHDL code for the FSM.
2.Design a finite state machine that detects two consecutive zeros (0s).
3.Design a sequence detector that detects the sequence 1, 0, 1, 1, 0 using a finite state machine.