1. An SEdit schematic showing a properly constructed complex CMOS gate of your function.
2. Annotate the schematic with proper sizing parameters for each transistor to achieve behavior similarto a symmetric inverter
3. The proper Euler Paths that produce the best layout for the gate.
4. A design-rule correct layout according to your Euler Paths. Include a calculation of the area.- Also, submit a design-rule correct LEdit layout.
5. Use the information from your design-rule correct layout to adjust dimensions in the TSpice file.Make sure the final result you submit for all calculations and simulations is based on the actual layout. Submit the sizing calculations and the TSpice file.
6. The voltage transfer curve for your complex gate obtained using TSpice.
7. Hand calculations for the rise and fall times. Assume that the gate is driving one of the inputs of a similar gate.
8. Hand calculations for the rising and falling propagation delay ranges. Maintain the same assumption from step 7. show what input combinations produce the maximum and minimum propagation
9. TSpice simulations for the values calculated in steps 7 and 8. Use the 1.25 m technology file that came with TSpice and use the same values for all steps of the and beta =2.4 .