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  Theory of CMOS Logic Gates and Current-Voltage Relationships

Introduction:

Figure below exhibits the characteristics of n-type and p-type and improvement mode MOS transistors. The polarity of currents and voltages are shown for both types of transistor. This can be observed that the voltages are positive in n-type and negative in p-type (comprising the threshold voltage). It can also be seen that current flow through the transistors is from drain to source in the n-type device but from source to drain in the p-type device.

The circuits that are of interest, which execute from a single-rail supply, the p-type device will appear upside-down in circuit configuration with respect to n-type device. If the convention is adopted for the p-type device to use the source-to-gate voltage, VSG, and the source-to-drain voltage, VSD, as shown in figure below, then the similar set of equations can be employed to characterise both improvement mode devices where all voltages, comprising the threshold voltage VT are considered positive.

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Figure: Sign Conventions for n-type and p-type MOS Transistor

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Figure: Characteristics of both kinds of MOS Transistors

Current-Voltage Relationships:

A conducting channel is made in the improvement-mode device if VGS > VT. When the above sign convention is adhered to, the similar set of equations can be employed to explain the current-voltage relationship for both p-type and n-type transistors.

Non-Saturation Region:

n-channel:

ID = Kn [2(VGS - VT) VDS – V2DS]

p-channel:

ID = Kp [2(VGS - VT)VSD – V2SD]

Saturation Region:

n-channel:

ID = Kn (VGS - VT)2

p-channel:

ID = Kp (VSG - VT)2

The CMOS Inverter:

The CMOS inverter is made by joining a p-type and n-type transistor and a transistor in series, with the p-type inverted to execute from a single-voltage supply, as shown in figure below. The transfer characteristic of inverter is too shown. The critical logic voltages, stated at the points on the characteristic where the slope is -1, can be adjusted by modifying the relative aspect ratios W/L of the two transistors. Usually they are set at 20 to 25% and 75 to 80% of the supply voltage.

When the nominal logic voltages are stated as VL = 0V and VH = VDD then:

When the input voltage is LO with Vi = 0V the gate-source voltage of lower n-type transistor, T1, is zero that is below the threshold voltage, VT, and therefore this transistor is non-conducting or OFF. On other hand, the p-type transistor, T2, that is upside down, has a VGS = -VDD or VSG = VDD that is well above the threshold voltage and therefore this transistor is completely conducting or ON. Transistor T2 can then supply current to any load needed and with full conduction will give an output voltage VO → VDD or the logic HI level.

Whenever the input voltage is HI with Vi = VDD the gate-source voltage of p-type transistor is zero and hence T2 is OFF, whereas the gate-source voltage of the n-type transistor is equivalent to VDD and therefore transistor, T1, is completely conducting and is ON. With an adequately high trans conductance parameter the output voltage can be made much low and hence VO → 0V or logic LO. This outcome in an inverting action is confirmed by the table shown below:

INPUT                  T1          T2          OUTPUT         

Vi = 0V,     LO      OFF         ON          Vo → VDD, HI

Vi = VDD,   HI       ON         OFF         Vo → 0V, LO

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Figure: Schematic figure and Transfer Characteristic of a CMOS Inverter

The CMOS NOR Gate:

The schematic figure of a 2-input CMOS NOR gate is as shown in figure below. It can be seen that the transistors are driven in p-type cum n-type pairs through each input. Basically, the n-type driving transistors are joined in parallel whereas the p-type load transistors are joined in series. In each pair, either the n-type transistor will be ON whereas the p-type is OFF, or vice-versa, based on the logic state of the related input. The table of conduction states for all transistors can be drawn up to establish the logic function executed by the gate, as shown below. The state of output can be established by treating the transistors that are ON as equivalent to closed switches and those which are OFF as equal to open switches. This is as shown, for example, in figure below for case where Input A is HI and Input B is LO.

IN A        IN B        T1        T2        T3        T4        OUT

LO            LO         OFF        ON       OFF      ON        HI

LO            HI          OFF        ON       ON       OFF       LO

HI             LO         ON         OFF     OFF       ON        LO

HI             HI          ON         OFF      ON       OFF       LO

The CMOS NAND Gate:

The schematic figure of a 2-input CMOS NAND gate is as shown in figure below. This can be seen that the structure is identical to the NOR gate, however in this case the n-type driving transistors are joined in series whereas the p-type load transistors are joined in parallel. Transistors are again driven in n-type cum p-type pairs with one transistor ON whereas the other is OFF. The table of conducting states of transistors for all logic combinations of the inputs is shown below. The switch equivalent is as shown for the case where Input A is HI and Input B is LO in figure below.

IN A        IN B        T1        T2        T3        T4        OUT

LO            LO         OFF        ON       OFF      ON        HI

LO            HI          OFF        ON       ON       OFF       HI

HI             LO         ON         OFF     OFF       ON        HI

HI             HI          ON         OFF      ON       OFF       LO

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Figure: Schematic figure of a 2-input CMOS NOR Gate

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Figure: Equivalent Circuit of NOR Gate with IN A = HI and IN B = LO

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Figure: Diagram of a 2-input CMOS NAND Gate

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Figure: Equivalent Circuit of the NAND Gate with IN A = HI and IN B = LO

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