Introduction:

In common, an instrumentation amplifier is needed to amplify the difference among two input signals or voltages, V₁ and V₂ as shown in figure below. Though, as discussed, in case of many transducers there is frequently a potential at both inputs existed whenever the input parameter to be measured is zero. This signal is similar at both inputs and is exist regardless of the value of input parameter. This signal is stated as the Common-Mode input signal, V_ic and must make no contribution to the output voltage of amplifier. On other hand, if the value of input parameter is non-zero, then the potential at one input terminal will rise, while that at other input terminal will reduce proportionately, giving a difference in potentials at the two input terminals. This difference in two input potentials is stated as the Differential-Input signal, V_id. Figure below exhibits the common-mode voltage as applied centrally to both input terminals of the amplifier whereas the differential voltage is considered split among the two inputs as half the differential potential one each side, V_id /2. This is applied as a positive sense signal to non-inverting input of the amplifier and as a negative sense signal to the inverting input of amplifier.

Figure: Differential and common Mode Inputs to a Differential Amplifier

The distribution of common-mode and differential mode signal is stated in figure below. The potentials shown symbolize steady-state or dc levels, however could equally be time-varying or dynamic signals. For illustration if the signal of interest to be evaluated were the Electrocardiogram received from two electrodes positioned on the surface of body, then this would make the differential input signal. The common-mode signal in this scenario is frequently composed of mains interference from the electricity supply. This gives mount to an unwanted signal at the input of amplifier that should be rejected in favour of the wanted differential signal that must be amplified. The capability of amplifier to discriminate against the common- mode signal and prevent it from forming any contribution to output voltage of the amplifier is known as Common Mode Rejection. Ideally, the common-mode input signal must generate no response at the output however in practice it does make certain contribution. A figure of merit employed to quantify the extent of an amplifier’s ability to refuse or supress the common-mode input signal is the CMRR or Common-Mode-Rejection-Ratio of the amplifier.

Figure: The Distribution of differential and common mode Input Voltages

Common-Mode-Rejection-Ratio:

From the above definitions and from both the figure above we have:

V₁ = V_ic + (V_id/2) and V₂ = V_ic – (V_id/2)

And hence,
 
 V_id = V₁ -  V₂ and V_ic = (V₁ + V₂)/₂

If the differential amplifier were ideal, it would repress the common-mode component of the input signal and hence the output consists of no contribution from the common mode input and output voltage would simply be given as:

V_o = A_d (V₁ – V₂) = A_d V_id

Where A_d is the differential gain of the amplifier as provided. Though, in practice the amplifier doesn’t fully refuse the common mode component of the input signal and this as a result forms some contribution to the output. The common-mode gain, A_c can thus be specified therefore the output voltage of the amplifier is given as:

V_o = A_d V_id + A_c V_ic

Ideally A_c →0 however in practice A_c << A_d however is finite.

The measure of ability of the amplifier refuse the common mode input component, V_ic , in favour of the differential component is, the Common-Mode-Rejection Ratio or CMRR of the amplifier. This is stated as:

CMRR = A_d/A_c; ideally A_c → 0 and CMRR → ∞

Then by expressing the common-mode gain in terms of differential gain we encompass:

A_c = A_d/CMRR

In this condition,

V_o = A_d V_id + (A_d/CMRR) V_ic

The left hand word is the wanted output signal whereas the right hand term is essentially an error component. Error in the output is then given as the ratio of such components:

ε = [(V_ic/CMRR)/V_id] = (1/CMRR) (V_ic/V_id) x 100 %

In order to get a desired fractional error ε the needed CMRR is:

CMRR = (1/ε) (V_ic/V_id)

For illustration, if V_ic=1V and V_id =1mV, then for 1% error we require:

CMRR = (1/0.01) x (1/10^-3) = 10⁵ = 100 dB

This is substantial however usual of the CMRR needed in bio-amplifiers.

Determining the factors of CMRR:

Let consider again the standard 3 op-amp instrumentation amplifier as illustrated below:

Figure: The standard 3 op-amp Instrumentation amplifier

We know that,

V_o1 = [1 + (R₂/R₁) V₁] – (R₂/R₁) V₂ and V_o2 = [1 + (R₂/R₁) V₂] – (R₂/R₁) V₁

For the input stage:

If,

From this it can be observe that the common-mode signal gets amplified by the factor of just unity on both sides of the initial phase of this amplifier structure. On other hand, the differential input component on each and every side of the amplifier receives a gain of (1+2 R₂/R₁). This enhances the total common mode rejection ratio of the amplifier since it boosts the wanted differential signal as compared to the unwanted common-mode signal prior to being passed to output phase that performs the differential input-to-single-ended output. In the final phase we have:

V_o = (R₄/R₃) (V_o1 = V_o2)

On substituting gives:

And hence finally:

V_o = (R₄/R₃) [1 + 2(R₂/R₁)] V_id

This exhibits that in the final phase, beneath perfect conditions, the common-mode signal is refused completely by the amplifier, whereas the differential signal gets an additional gain of R₄/R₃. This implies that beneath such ideal conditions this amplifier structure has infinite common-mode rejection ratio.

In practice, obviously, conditions are not ideal and the CMRR of amplifier is finite. There are 3 major factors that act to restrict the CMRR attainable:

a) Mismatch in the input impedances and source of the amplifier
b) Manufacturing tolerances, in gain-determining resistors
c) Finite CMRR of an individual operational amplifier.

Source and Input Impedance Mismatch:

The input phase of any instrumentation amplifier can be modelled as shown in figure below. Each input has impedance related with the corresponding source. For illustration the impedance of electrodes employed to measure an ECG signal is important and will as well exhibit a variation from one electrode to other, and hence there is a mismatch among the two source impedances. The amplifier includes impedance among each input terminal and ground that is referred to as the common-mode input impedance. This can as well be slightly different on each and every side. Ultimately, there is finite impedance among the two input terminals of the amplifier, termed to as the differential input impedance. When a common-mode signal only is applied to the amplifier inputs, through various source impedances to various input common-mode impedance on each and every side, then the signal appearing at two input terminals of the amplifier will be slightly dissimilar. This signifies that the mismatch in impedances leads to the applied common-mode input signal being efficiently transformed into a signal containing a differential component at the input to the amplifier. This differential component will then be given full differential gain in passing via the amplifier and will give mount to an error in the total output signal that is due to the unwanted common-mode input signal that has not been fully refused.

Figure: The Equivalent circuit of an Instrumentation Amplifier Input

The principle of superposition can be employed to establish the potential at inverting and non-inverting inputs of the amplifier. When the input impedance of amplifier itself is taken as ideal, then no current flows into it however is confined to the network of impedances. Consider the condition where the input potential V₁ is applied with V₂ = 0V and hence the latter input can then be considered grounded.

In this condition, the potential at non-inverting input, V⁺ and that at inverting input is due to the input, V₁ which can be found as:

When the common-mode input impedances encompass a tolerance of ± ΔC however are intended to be purely resistive where possible and the source impedances encompass a mismatch of ± ΔS then the worst case mismatch occurs when:

Z_SA = Z_S (1 + ΔS)
Z_SB = Z_S (1 - ΔS)
Z_CA = R_C (1 – ΔC)
Z_CB = R_C (1 + ΔC)

Then with,

V₁ = V_iC + (V_id/2)
V₂ = V_iC - (V_id/2)
         
When such replacements are made, the potential at the input of amplifier from the network can be obtained in form of:

V⁺ - V^- = A_cZ V_iC + A_dZ V_id

CMRR due to the input impedance mismatch can then be stated in the usual way and whenever the suitable analysis is taken out it can be illustrated that:

With small value of ΔC this can be stated in Decibels as:

CMRR _ΔZ|_dB = 20 log₁₀ R_C/|Z_S| + 20 log₁₀ [1/2(Δ_C + Δ_S)]

When all the other factors influencing the total CMRR of the amplifier can be taken out as ideal then the mismatch in impedance values will find out the CMRR that can be attained by the instrumentation amplifier in refusing unwanted common mode signals.

Illustration:

An ECG recording amplifier is employed with high impedance electrodes in the portable application. The smallest component of interest in ECG signal consists of amplitude of 1mV at point of pick-up. This is desired to sustain a minimum signal-to-interference ratio of 20dB whenever observing this component. Due to interference in recording environment mains supply hum at a frequency of 50Hz is existed on the patient’s body at amplitude that can be as high as 2Vrms.When the recording electrodes encompass an impedance 0.5MΩ ± 20% at 50Hz, find out the value of common-mode input impedance needed in the instrumentation amplifier employed.

Solution:

The differential input signal level should be taken as V_id = 1mV peak

Common-mode interfering signal is the mains hum at rms level of 2V
The peak value of common-mode signal is then V_ic = 2 x √2 = 2.83V

The signal-to-interference ratio needed at the output of amplifier is 20dB that corresponds to an absolute value of 10. This implies that the error in the signal observed must be less than 1 part in 10 or 1/10 = 0.1. Then,

CMRR = (1/ε) (V_iC/V_id) = (1/0.1) x (2.83/10^-3) = 2.83 x 10⁴
 
If CMRR is taken out as being limited merely by impedance mismatch, then this entails that:

CMRR ΔZ = [R_C(1 – Δ²C)]/[2Z_S (Δ_C + Δ_S)] = 2.83 x 10⁴

The tolerance in electrode impedance is ±20% and hence Δ_S = 0.2. When a 5% tolerance in the resistors is supposed then Δ_C = 0.05. This gives:

R_C/ (2 x 0.5 x 10⁶ x 0.25) = 2.83 x 10

And hence,

R_C = 0.25 x 10⁶ x 2.83 x 10⁴ ≈ 7 x 10⁹

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