Static and dynamic hazards in logic circuits
Describe static & dynamic hazards in logic circuits?
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If for a short period of time circuits goes to some distinct logic level then this is supposed to have then it is known as static hazard for example If the final logic value of output of a specific circuit becomes one even if this is supposed to be zero then this is called Static-0 Hazard and vice versa. Dynamic Hazard is the one wherein the circuit output goes to some other logic level more than once then in the end settling down to some proper level.
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